Translating the Instructional Processor from VHDL to Verilog

Ronald J Hayne

Abstract


An Instructional Processor has been developed for use as a design example in an Advanced Digital Systems course.  The system was originally modeled in VHDL and was simulated using Xilinx design tools to demonstrate operation of the processor.  The design model can also be synthesized and implemented in hardware on a field programmable gate array.  The goal of this project was to translate the Instructional Processor into the Verilog hardware description language, while maintaining the same operational characteristics.  VHDL and Verilog are IEEE standard languages used for the development and testing of hardware designs.  Used correctly, these languages describe hardware constructs, which can be implemented using computer aided design tools.  These synthesis tools have their own design guidelines, which align modelling techniques with standard library modules such as multiplexers and registers.  The process of translating the Instructional Processor from VHDL to Verilog has also resulted in several key insights and lessons learned.  These range from correct use of signal types and library functions to important differences in simulation versus synthesis tools.  The Instructional Processor has been successfully translated from its original VHDL to an equivalent Verilog model.  By focusing on describing each hardware component, rather than just revising syntax, the design maintained its functional integrity.  The hardware synthesized by the Xilinx tools was very consistent in both device utilization and system timing.  The project was a success and the Instructional Processor continues to be a valuable instructional tool, now available in two languages.

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The ASEE Computers in Education (CoED) Journal
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